Location : Bengaluru / Bangalore
Experience : 2 to 5 Year(s)
Strong working knowledge of VHDL / Verilog and SystemVerilog and SystemVerilog Assertions Experience with Assertion - based Formal verification TCL script development within these tool shells in addition to running / analysing / debugging designs . Expertise in Formal Verification products like Mentor Formal , Jasper or any other Formal products is highly desirable Low power verification techniques using UPF and CPF is a plus Exposure to static timing analysis (STA) flows involving SDC is a plus Knowledge of constrained random verification methods is a plus . General / soft skills:
Corporate Resources is a national HR service provider servicing world class companies across the globe. Started in 2004, the company has grown into a full spectrum HR services provider for clients worldwide. It has helped generate career opportunities for thousands of individuals in the countries, and has worked for over Fortune 500 organizations.
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